1. Field of the Invention
The invention relates to a method of manufacturing a semiconductor device having a trench isolation structure and more particularly to a method of manufacturing a nonvolatile semiconductor memory having a trench isolation structure.
2. Description of the Related Art
To form a semiconductor device, a plurality of devices is formed on one semiconductor substrate so as to function as the semiconductor device. Formation of a plurality of devices on the same substrate requires electrical isolation of the devices from one another. LOCOS, a trench isolation structure or the like is generally used as a method of isolating devices. Of these methods, the trench isolation structure is used as the method of isolating devices for a micro-device, because the trench isolation structure does not have to form a thick thermal oxide film and is effective for microfabrication, as distinct from LOCOS. Semiconductor devices having the trench isolation structure are of various types. Semiconductor devices include a nonvolatile semiconductor memory having a floating gate, such as a DRAM, an SRAM, an EPROM or an EEPROM.
Semiconductor devices having a conventional trench isolation structure include a nonvolatile semiconductor memory comprising a memory cell and a peripheral circuit as shown in FIG. 24, for example. The memory cell and the peripheral circuit have the respective trench isolation structures, and edges of the trench isolation structures are angular as shown in a partially sectional view of FIG. 25. The nonvolatile semiconductor memory is manufactured in the following manner. First, a silicon oxide film 102 of 10 nm thick is grown on a main surface of a p type (001) silicon substrate 101 by use of thermal oxidation. Subsequently, a silicon nitride film 103 of 200 nm thick is deposited on the silicon oxide film 102 by reduced pressure CVD method. Next, a resist 104 is formed into a desired pattern by photolithography, and then the silicon nitride film 103 is etched by using the resist 104 as a mask (see FIG. 26).
Subsequently, the silicon oxide film 102 is etched by using the resist 104 as a mask, whereby trenches 105 each having a depth of about 400 nm are formed in the surface of the silicon substrate 101, and then the resist 104 is removed (see FIG. 27).
Furthermore, a silicon oxide film 106 of 600 nm thick is deposited by using CVD, whereby the trenches 105 are filled with the silicon oxide film 106 (see FIG. 28). Then, the surface of the silicon oxide film 106 is polished by chemical mechanical polishing (CMP), and a predetermined amount of the silicon oxide film is etched by using a hydrogen fluoride (HF) aqueous solution. Subsequently, the silicon nitride film 103 is removed by using heated phosphoric acid, and then the silicon oxide film 102 is removed by using the hydrogen fluoride aqueous solution as an etchant, whereby trench isolations 107 are formed (see FIG. 29).
Next, a resist 108 is formed into a desired pattern by photolithography. Then, by using the resist 108 as a mask, phosphorus ions of 2xc3x971013 cmxe2x88x922 are implanted with energy of 1.2 MeV in the silicon substrate 101, and subsequently phosphorus ions of 2xc3x971012 cmxe2x88x922 2 are implanted with energy of 200 keV in the silicon substrate 101. After that, heat treatment takes place at a temperature of 1000xc2x0 C. under a nitrogenous atmosphere, whereby an n well region 109 is formed (see FIG. 30).
Furthermore, a silicon oxide film 110 of 10 nm thick, which is to constitute a tunnel oxide film of a memory transistor, is grown by thermal oxidation. Then, phosphorus-doped polycrystalline silicon 111 of 100 nm thick and a silicon oxide film 112 of 100 nm thick are deposited on the silicon oxide film 110 by reduced pressure CVD method. After that, a resist is formed into a desired pattern by photolithography, and then the silicon oxide film 112 is etched by using the resist as a mask. After the resist is removed, the phosphorus-ions-doped polycrystalline silicon 111 is etched. Subsequently, ions of arsenic of 2xc3x971015 cmxe2x88x922 are implanted with energy of 40 keV by ion implantation. After that, heat treatment takes place at a temperature of 850xc2x0 C. for 30 minutes under a nitrogenous atmosphere, whereby the ions of arsenic are activated and thus n type diffused layers 113a and 113b are formed (see FIG. 31).
Subsequently, a silicon oxide film 114 of 800 nm thick is deposited by reduced pressure CVD method, and heat treatment takes place at a temperature of 850xc2x0 C. for 30 minutes under a nitrogenous atmosphere (see FIG. 32). Then, the silicon oxide film 114 is etched, whereby the surface of the phosphorus-ions-doped polycrystalline silicon 111 is exposed (see FIG. 33).
Subsequently, a three-layer insulating film 115 comprising a silicon oxide film of 5 nm thick, a silicon nitride film of 10 nm thick and a silicon oxide film of 5 nm thick is deposited by reduced pressure CVD method (see FIG. 34).
Next, the memory cell is coated with a resist by photolithography, and the three-layer insulating film 115, the phosphorus-ions-doped polycrystalline silicon 111 and the silicon oxide film 110 on the substrate surface, which are to constitute the peripheral circuit, are removed. After that, the resist is removed (see FIG. 35).
After that, a silicon oxide film 116 of 30 nm thick, which is to constitute a gate oxide film of a transistor of the peripheral circuit, is grown by use of thermal oxidation (see FIG. 36). In this case, in the memory cell, the silicon nitride film in the three-layer insulating film 115 prevents thermal oxidation of an underlayer.
Subsequently, phosphorus-ions-doped polycrystalline silicon 117 of 200 nm thick and a silicon oxide film 118 of 200 nm thick are deposited by reduced pressure CVD method. A resist is formed into a desired pattern by photolithography, then the silicon oxide film 118 is etched by using the resist as a mask, and then the resist is removed. After that, the phosphorus-ions-doped polycrystalline silicon 117, which is to constitute a gate electrode of the transistor of the peripheral circuit, is etched by using the silicon oxide film 118 as a mask. At the same time, the phosphorus-ions-doped polycrystalline silicon 117, which is to constitute a control gate of the memory transistor, is etched, and then the resist is removed (see FIG. 37).
A resist is formed on the peripheral circuit by photolithography, and then the three-layer insulating film 115 and the phosphorus-ions-doped polycrystalline silicon 111 are etched by using the silicon oxide film 118 of the memory cell as a mask, whereby a floating gate electrode 111 of the memory transistor is formed.
Next, a resist is formed into a desired pattern by photolithography, then ions of arsenic of 3xc3x971015 cmxe2x88x922 are implanted with energy of 50 keV by using the resist as a mask, and then the resist is removed. A resist is again formed into a desired pattern by photolithography, and then ions of BF2 of 3xc3x971015 cmxe2x88x922 are implanted with energy of 30 keV by using the resist as a mask. After that, heat treatment takes place at a temperature of 800xc2x0 C. for 30 minutes under a nitrogenous atmosphere, whereby an n type diffused layer 119 of an n-channel transistor of the peripheral circuit and a p type diffused layer 120 of a p-channel transistor thereof are formed (see FIG. 38).
Furthermore, boron phosphorus glass 121 of 1 xcexcm (1000 nm) thick is deposited by CVD. After that, heat treatment takes place at a temperature of 850xc2x0 C. for 30 minutes under a nitrogenous atmosphere, whereby the boron phosphorus glass 121 is thermally shrunk. Subsequently, a resist is formed into a desired pattern by photolithography, and then the boron phosphorus glass 121 is etched by using the resist as a mask, whereby a contact hole is opened. After that, an aluminum-silicon-copper (Alxe2x80x94Sixe2x80x94Cu) alloy film 122 is deposited by sputtering. Next, a resist is formed into a desired pattern by photolithography, and then the aluminum-silicon-copper (Alxe2x80x94Sixe2x80x94Cu) alloy film 122 is etched by using the resist as a mask, whereby aluminum-silicon-copper (Alxe2x80x94Sixe2x80x94Cu) wiring 122 is formed (see FIG. 39). The semiconductor device having the trench isolation structure can be obtained through the above-described steps and processes.
A memory function of the nonvolatile semiconductor memory having the floating gate will be described below with reference to FIG. 40 showing an enlarged sectional view of the memory cell shown in FIG. 24. The nonvolatile semiconductor memory stores information (data) in the memory cell in accordance with whether electrons are injected into the floating gate or ejected from the floating gate. In a status in which electrons are injected into the floating gate 111, a threshold voltage of the memory cell takes on a given high value Vthp. This status is called a program status. In this case, data xe2x80x9c1xe2x80x9d is stored in the memory cell. Since the electrons stored in the floating gate 111 are not semipermanently erased in the program status, the stored data is also semipermanently held. In a status in which electrons are ejected from the floating gate 111, the threshold voltage of the memory cell takes on a given low value Vthe. This status is called an erase status. In this case, data xe2x80x9c0xe2x80x9d is stored in the memory cell. The data stored in the memory cell can be read by detecting whether the memory cell is in the program status or the erase status.
At the program time, a high voltage Vpp (generally about 20 V) is applied to the control gate 117, whereby the n type diffused layers 113a and 113b and the substrate 101 are grounded. Thus, electrons are generated in a channel formed in a region between the n type diffused layers 113a and 113b, an energy barrier formed by the tunnel insulating film 110 is tunneled, and thus the electrons are allowed to enter into the floating gate 111. As a result, the threshold voltage of the memory cell rises.
At the erase time, the high voltage Vpp (generally xe2x88x9220 V) is applied to the control gate 117, whereby the n type diffused layers 113a and 113b and the silicon substrate 101 are grounded. Thus, a tunnel phenomenon allows electrons to exit from the floating gate 111 to the silicon substrate 101. As a result, the threshold voltage of the memory cell drops.
At the time of a read operation of a selected memory transistor, for example, a voltage of 3.3 V (Vcg=3.3 V) and a voltage of 3.3 V are applied to the control gate 117 and a drain (the n type diffused layer 113a), respectively, whereby a source (the n type diffused layer 113b) and the silicon substrate 101 are grounded. When Vthp greater than 3.3 (V) greater than Vthe, a current does not pass between the source and the drain of the memory transistor in the program status, whereas a current passes between the source and the drain of the memory transistor in the erase status.
At the time of the above-mentioned read operation, in any memory transistor other than the selected memory transistor, the control gate 117 is grounded (Vcg=0 V), and a voltage of 3.3 V is applied to the drain (the n type diffused layer 113a), whereby the source (the n type diffused layer 113b) and the silicon substrate 101 are grounded. When Vthp greater than Vthe greater than 0 (V), a current does not pass between the source and the drain of the memory transistor regardless of the program status or the erase status because Vcg=0 V.
Therefore, whether each memory cell is in the program status or the erase status can be detected in accordance with whether or not a current passes between the source and the drain of the selected memory transistor.
However, it is known that the semiconductor device having the conventional trench isolation structure has the following disadvantage. That is, the shape of the edge of the trench isolation structure is xe2x80x9cangularxe2x80x9d as shown in FIG. 25, thus the edge is intensively subjected to a stress and an electric field, and this causes deterioration in insulating properties and reliability of insulating films of a memory cell transistor and a peripheral transistor. Thus, the following problems arise. For example, in the memory cell, a phenomenon occurs in which electrons stored in the floating gate are prone to exit from the floating gate. In the peripheral transistor, a transistor capable of withstanding a high voltage required for write and erase cannot be formed, and an oxide film cannot have a sufficiently long life under the load of high voltage.
Therefore, various attempts to control the shape of the trench edge have been heretofore made in order to prevent the trench edge from intensively incurring a stress and an electric field. For example, one attempt is a method which includes forming a mask on a semiconductor substrate; forming an opening for forming a trench in the mask layer; then performing isotropic etching to a shallow depth through the opening; and subsequently performing anisotropic etching to a predetermined depth, thereby forming a trench for isolating devices (see Japanese Laid-open Patent Publication No. 2-174140). The trench having the opening in the upper portion thereof is formed by the above-mentioned method. However, it is relatively difficult to adjust setting of conditions for isotropic etching, or the like.
Another attempt is as follows. Methods of forming a connect hole such as a contact hole for connecting metal wiring include a method which includes changing a sectional shape of a resist pattern from a cylindrical shape into a tapered shape; and tapering an overall insulating film by etching (see Japanese Laid-open Patent Publication No. 5-326357). However, the method causes etching to taper the overall connect hole, and moreover the method requires a complicated process such as two steps of exposure.
Still another attempt is a method of manufacturing a semiconductor which includes forming a trench through a semiconductor oxide layer and a semiconductor main surface by dry etching; and successively rounding an upper edge of the trench by wet etching (see Japanese Laid-open Patent Publication No. 2000-21970). The rounded upper edge of the trench prevents the edge from intensively incurring an electric field.
However, a procedure is prone to be complicated because wet etching takes place in succession to dry etching.
A further attempt is a method of manufacturing a semiconductor device which includes thermally oxidizing an inner wall of a trench and thereby controlling a distance between facing corners of an upper edge of the trench (see Japanese Laid-open Patent Publication No. 9-321134). The method allows preventing the trench isolation edge from intensively incurring an electric field.
However, a process is prone to be complicated because the method requires a step of thermally oxidizing the inner wall of the trench. Moreover, the control of thermal oxidation or the like involves difficulties.
It is therefore an object of the invention to provide a method of manufacturing a semiconductor device which can obtain a semiconductor device having a trench isolation for preventing a trench edge of a trench isolation structure from intensively incurring an electric field and a stress, by means of a simple process such as dry etching without the use of a complicated process such as wet etching or thermal oxidation.
In accordance with one aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a trench isolation structure. The method of manufacturing a semiconductor device having a trench isolation structure includes:
patterning a mask film on a semiconductor substrate;
forming a trench by etching the semiconductor substrate by use of the mask film;
filling the trench with an insulating film by repeating depositing the insulating film in the trench and etching the insulating film by sputter etching;
removing the mask film; and
removing the insulating film by etching a predetermined amount of the insulating film filled in the trench.
According to the sputter etching in filling the trench with the insulating film, an edge between a surface of the substrate and an inner wall surface of the trench forms an inclined surface to the surface of the substrate.
The shape of the trench edge will be more specifically described. The edge between the inner wall surface of the trench and the surface of the semiconductor substrate may comprise one or more inclined surface to the surface of the semiconductor substrate. Therefore, the edge may have a polyhedral shape such as a so-called chamfered shape. Moreover, the edge may include one or more concave or convex surface. Therefore, the edge may partly include a curved surface portion of the concave or convex surface.
The sputter etching may include controlling a flow rate of a flowing deposition gas.
The mask film may include a silicon oxide film and a silicon nitride film formed on the silicon oxide film.
In other aspect of the present invention a method of manufacturing a semiconductor device having a trench isolation structure includes:
depositing a silicon oxide film and a silicon nitride film in sequence on a semiconductor substrate;
patterning a resist film on the silicon nitride film; forward tapering the silicon nitride film and the silicon oxide film;
forming a trench by etching the semiconductor substrate by using the silicon nitride film as a mask;
filling the trench with an insulating film;
removing the silicon nitride film; and
removing the insulating film by etching a predetermined amount of the insulating film filled in the trench.
The step of forming the trench may include etching the forward-tapered silicon oxide film and the semiconductor substrate in sequence.
Thus, an edge between a surface of the semiconductor substrate and an inner wall surface of the trench forms an inclined surface to the surface of the semiconductor substrate.
Before forming the trench, the silicon oxide film and the silicon nitride film are stacked in sequence on the semiconductor substrate as shown in FIG. 22. An etched surface exposed by anisotropic etching in a depth direction is slightly inclined to a vertical surface. On the etched surface, the silicon oxide film whose top surface is not coated with the silicon nitride film is exposed and faced to diagonally upward direction. The etched surface is called a forward-tapered surface because the etched surface has an exposed surface diagonally upward. In this case, the respective etched surfaces of the silicon nitride film and the silicon oxide film do not necessarily require the same inclination.
The step of forward tapering the silicon nitride film and the silicon oxide film may include etching using the resist film as a mask, while controlling a flow rate of a deposition gas flowing through the silicon nitride film and the silicon oxide film.
The insulating film filling in the trench may be a silicon oxide film.
The semiconductor device having the trench isolation structure may be a nonvolatile semiconductor memory.
As described in detail above, according to the method of manufacturing the semiconductor device according to the invention, an edge between an inner wall surface of a trench and a surface of a semiconductor substrate can form an inclined surface to the surface of the semiconductor substrate. Therefore, the obtained semiconductor device can prevent the trench edge from intensively incurring a stress and an electric field and can thus improve properties of the device and reliability of an oxide film.
Moreover, according to the method of manufacturing a semiconductor device according to the invention, sputter etching includes controlling a flow rate of a flowing deposition gas. Therefore, the shape of the trench edge can be appropriately controlled.
Furthermore, according to the method of manufacturing a semiconductor device according to the invention, a multilayered film comprising a silicon oxide film and a silicon nitride film formed on the silicon oxide film is used as a mask film. Therefore, the multilayered film can also function as the mask film, while protecting the silicon oxide film.
According to the method of manufacturing a semiconductor device according to the invention, the edge between the inner wall surface of the trench and the surface of the semiconductor substrate can form the inclined surface to the surface of the semiconductor substrate. Therefore, the obtained semiconductor device can prevent the trench edge from intensively incurring a stress and an electric field and can thus improve properties of the device and reliability of an oxide film.
Moreover, according to the method of manufacturing a semiconductor device according to the invention, a flow rate of a flowing deposition gas is controlled. Therefore, the silicon nitride film and the silicon oxide film can be appropriately forward tapered.
Furthermore, according to the method of manufacturing a semiconductor device according to the invention, the insulating film filled in the trench is a silicon oxide film. Therefore, the insulating film can have good insulating properties.
Furthermore, according to a method of manufacturing a nonvolatile semiconductor memory according to the invention, in the memory cell of the obtained nonvolatile semiconductor memory, electrons stored in the floating gate can be held with stability. In the peripheral transistor, a transistor capable of withstanding a high voltage for write and erase can be formed, and moreover an oxide film can have a life long enough to treat a high voltage.